Computers , 1990 , 39 : 564 - 571 . 20 jiang j h . alternating - complementary locator and its use for error location in dual - modular redundancy with comparison structure 隨著要求高可用性和高可維護性的應用需求的增長,重試結構因其硬件開銷低而獲得了廣泛應用。
To tolerate faults , the techniques rely on redundant implementations , which are n - modular redundancy for building fault - tolerant hardware and n - version programming or recovery blocks method for building fault - tolerant software 容錯的技術在于采用冗余工具,也就是采用n模塊冗余構造容錯硬件,采用n版本編程或恢復塊方法構造容錯軟件。
To solve this problem , this paper presents a novel dual modular redundancy structure using complementary logic - alternating - complementary logic cl - acl switching mode . during error - free operation , the cl - acl structure operates by complementary logic mode . after an error is detected , it retries by alternating logic mode 在低電源電壓2 . 2v或更低或在0 . 1 m m vlsi工藝條件下,具有大于10 mev能級的宇宙中子流以高達20中子平方厘米小時到達地球表面時所引起的電路的隨機差錯率將是難以接受的。